报告题目：Advanced Topics in Computer Architecture
报告人：Per Stenstr?m, Professor, ACM/IEEE Fellow, member of Academia Europaea, the Royal Swedish Academy of Engineering Sciences and the Spanish Royal Academy of Engineering, Chalmers University of Technology, SWEDEN
As we move forward, the architecture of choice will consist of an increasing number of processing cores encompassing general ones as well as specialized. Main concerns for such heterogeneous multi/many-core architectures are to exhibit high performance within the constraints of the power being consumed. Key to this is to offer a productive interface to the software by offering primitives that can reduce the effort in writing parallel programs. To this end, the design of the memory system plays a key role.
In this course on Advanced Topics in Computer Architecture, the focus is on design issues related to on-chip memory hierarchies for heterogeneous multi/many-core systems and covers the following topics to improve power consumption and programmability.
Programmability enhancing techniques
Cache coherence and memory consistency
Thread-level speculation techniques
Run-time guided cache management
We lay the foundation for a family of techniques to enhance programmability by establishing the key notions of cache coherence and memory consistency. Armed with this, we review a number of approaches to enhance programmability. Thread-level speculation aims at unlocking parallelism by speculatively running sequential pieces of the program in parallel. The second family of techniques is transactional memory that offers primitives to the application interface that allows program pieces to execute atomically. Apart from reviewing different approaches to build such abstractions, we will also review applications of it. Finally, we will review some ongoing research efforts that explore how state-of-the-art task-based programming models can off-load the programmer from resource management by tightly integrating the run-time system with the architecture.
Power/energy saving cache/memory techniques:
Value locality and its opportunities
Cache compression techniques
Memory compression techniques
All these techniques leverage the observation that some values stored in memory are more prevalent than other. They seek to exploit that by storing and retrieving data more efficiently so as to use cache and memory resources more efficiently. We will see how this opens up for more effective memory hierarchies.
Value-aware caches store frequent values compactly to use cache resources more efficiently. Compression is the more general approach to track value locality in caches and memory. We go through a number of compression approaches and the specific issues that must be dealt with to allow for effectively applying them to cache and to memory.
Per Stenstr?m earned his PhD degree in computer engineering in 1990 from Lund University, Sweden. Since 1995 he is a Professor of Computer Engineering at Chalmers University of Technology, Sweden. His research interests are devoted to high-performance computer architecture and he has made major contributions to especially high-performance memory systems. He has authored or co-authored three textbooks and more than 130 publications in international journals and conferences and around ten patents. He is regularly serving program committees of major conferences in the computer architecture field and is an Associate Editor-in-Chief of the Journal of Parallel and Distributed Computing and a Senior Editor of ACM Transactions on Architecture and Code Optimization. He has been an editor of IEEE Transactions on Computers, IEEE Transactions on Parallel and Distributed Processing, the IEEE TCCA Computer Architecture Letters, and others. He co-founded the HiPEAC Network of Excellence funded by the European Commission. He has also acted as General and Program Chair for a large number of conferences including the ACM/IEEE Int. Symposium on Computer Architecture, the IEEE High-Performance Computer Architecture Symposium, the IEEE International Parallel and Distributed Processing Symposium and the ACM International Supercomputing Conference. He is a member of the ACM Europe Council, a Fellow of the ACM and the IEEE and a member of Academia Europaea, the Royal Swedish Academy of Engineering Sciences and the Spanish Royal Academy of Engineering.